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[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

Description: 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
Platform: | Size: 918528 | Author: ningning | Hits:

[VHDL-FPGA-Verilog] fifo_test.v.tar

Description: code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
Platform: | Size: 2048 | Author: Vikas | Hits:

[VHDL-FPGA-Verilog] asymmetric_fifo

Description: 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
Platform: | Size: 11264 | Author: claud | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
Platform: | Size: 62464 | Author: 张晗 | Hits:

[Software Engineering] fifo_template

Description: aes code with fifo control to memory
Platform: | Size: 9216 | Author: allen | Hits:

[Process-Thread] fifo

Description: 完成进程调度，页面置换算法中先进先出算法（FIFO）的源代码，对学习操作系统很有用的~-The completion of the process of scheduling, the page replacement algorithm in the FIFO method (FIFO) of the source code, useful for learning the operating system ~
Platform: | Size: 1024 | Author: jessie | Hits:

[USB develop] asfifodesign

Description: 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
Platform: | Size: 545792 | Author: 何正文 | Hits:

[OS Develop] FIFO

Description: 操作系统中的先进先出(FIFO)页面置换算法的C++源代码-Operating in the FIFO (FIFO) Page Replacement Algorithm for C++ source code
Platform: | Size: 1024 | Author: 段 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Platform: | Size: 10240 | Author: wei | Hits:

[VHDL-FPGA-Verilog] pgm

Description: uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
Platform: | Size: 205824 | Author: libin | Hits:

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

Description: 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
Platform: | Size: 1625088 | Author: xinsheng | Hits:

[Communication] MaxiCOM

Description: Unfortunately Microsoft has never paid much attention to the serial port. In the Windows API it is just regarded as a file, and in the first version (1.1) of the .NET framework (managed code) there was no support for serial communication. Fortunately, a new namespace - System.IO.Ports - has been added in version 2.0, which has made things much easier although there are still some problems. For example, it is not possible to control the FIFO in the UART. It is also not possible to tell when the transmitter serial register is empty, so it is almost impossible to control the modem control signals and send a break condition, but worst of all, Microsoft has put an 8 bit wide buffer on top of the 11-bit receiver FIFO and therefore destroyed the possibility for a precise Break, 9th bit and error detection. Besides, many of the examples in the help files are directly misleading and unnecessary complicated.
Platform: | Size: 366592 | Author: RAMAKERS_R | Hits:

[VHDL-FPGA-Verilog] fifo.v

Description: This the source code for FIFO -This is the source code for FIFO
Platform: | Size: 1024 | Author: Vishal katba | Hits:

[VHDL-FPGA-Verilog] fifo2

Description: 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
Platform: | Size: 372736 | Author: tangjieling | Hits:

[Software Engineering] source_code

Description: verilog code fifo memory usb
Platform: | Size: 4096 | Author: mohsen | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 速度高达130MHz 可实现高速数据采集 程序源码为Verilog-Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
Platform: | Size: 116736 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] 88fifovhdl

Description: 88位进出缓冲器8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-88 out of 8* 8-bit buffer fifo data buffer vhdl source Bianle Ge 8* 8-bit data buffer fifo vhdl source code is compiled through quartusII4.2 successful program. . Hope you share Nenggen
Platform: | Size: 2048 | Author: zhaorongjian | Hits:

[matlab] main

Description: Code Matlab of FIFO for 5 servers
Platform: | Size: 3072 | Author: dfccpy | Hits:

[DSP program] DSP_2812_SCI_232

Description: DSP2812串口通信编程，利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code
Platform: | Size: 389120 | Author: 黄晓军 | Hits:
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